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preliminary data sheet 12/8/03 1 lh7a400 preliminary data sheet 32-bit system-on-chip features ? arm922t? core: ? 32-bit arm9tdmi? risc core ? 16kb cache: 8kb instruction cache and 8kb data cache ? mmu (windows ce enabled) high performance (200 mhz) 80kb on-chip memory external bus interface ? 100 mhz ? asynchronous sram/rom/flash ? synchronous dram/flash ? pcmcia ? compactflash clock and power management ? 32.768 khz and 14. 7456 mhz oscillators ? programmable pll low power modes ? run (147 ma), halt (41 ma), standby (42 a) programmable lcd controller ? up to 1,024 768 resolution ? supports stn, color stn, ad-tft, hr-tft, tft ? up to 64,000 colors and 15 gray shades dma (10 channels) ?ac97 ?mmc ?usb usb device interface (usb 1.1) synchronous serial port (ssp) ? motorola spi? ? texas instruments ssi ? national microwire? three programmable timers three uarts ? classic irda (115 kbit/s) smart card interface (iso7816) dc-to-dc converters multimediacard? interface ac97 codec interface smart battery monitor interface real time clock (rtc) up to 60 general purpose i/os programmable interrupt controller watchdog timer jtag debug interface and boundary scan operating voltage ? 1.8 v core ? 3.3 v input/output (1.8 v i/o optional 1 ) 5 v tolerant inputs (except oscillator pins 2 ) operating temperature ? 0c to +70c commercial ? -40c to +85c industrial (with clock frequency reduction 1 ) 256-ball pbga or 256-ball cabga package description the lh7a400, powered by an arm922t, is a com- plete system-on-chip with a high level of integration to satisfy a wide range of requirements and expectations. this high degree of integration lowers overall sys- tem costs, reduces develo pment cycle time and accel- erates product introduction. motorola spi is a trademark of motorola, inc. national semiconductor microwire is a trademark of national semiconductor corporation. windows ce is a trademark of microsoft corporation. notes: 1. under development. results pe nding further characterization. 2. oscillator pins r13, t13, p15, and p16 are 1.8 v 10%
lh7a400 32-bit system-on-chip 2 12/8/03 preliminary data sheet figure 1. lh7a400 block diagram lh7a400-1 oscillator, pll1 and pll2, power management, and reset control interrupt controller real time clock 14.7456 mhz 32.768 khz synchronous dynamic ram controller (sdmc) pcmcia/cf controller color lcd controller 80kb sram lcd ahb bus static (asynchronous) memory controller (smc) external bus interface arm922t advanced peripheral bus bridge dma controller advanced high-performance bus (ahb) advanced perpheral bus (apb) advanced lcd interface general purpose i/o (60) synchronous serial port timer (3) battery monitor interface usb device interface watchdog timer irda interface uart (3) multimediacard interface smart card interface (iso7816) audio codec interface advanced audio codec (ac97) dc to dc interface (2)
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 3 table 1. functional pin list pbga pin cabga pin signal description reset state standby state output drive g7 c10 vdd i/o ring power f1 f9 k7 f11 m1 f14 m5 g8 t6 h13 r14 j9 m14 k15 j11 l7 j12 n6 f13 n8 b14 n12 e10 n13 b8 p11 h7 b8 vss i/o ring ground g3 c6 k4 d5 n5 d13 p6 e8 t14 f7 r16 g13 n16 h9 k13 j14 h9 k7 c15 l8 a11 l10 e8 l12 a5 m11 f7 m14 e1 c4 vddc core power j4 d7 p3 d10 t8 f4 k9 f10 l13 j4 e15 j8 d12 k8 a7 l6 h5 g7 vssc core ground m3 h4 l9 h8 t10 l4 n15 l9 h12 n3 b15 n7 c9 n10 g6 r5
lh7a400 32-bit system-on-chip 4 12/8/03 preliminary data sheet r11 p12 vdda analog power for pll n12 m10 p12 r13 vssa analog ground for pll t11 n11 d3 e4 npor power on reset input input h6 d1 nureset user reset; should be pulled high for normal or jtag operation. input (schmitt) input d4 e2 wakeup wake up input (schmitt) input e4 f2 npwrfl power fail signal input (schmitt) input c2 d2 nextpwr external power input (schmitt) input r13 r14 xtalin 14.7456 mhz crystal oscillator pins. an external clock source can be connected to xtalin leav- ing xtalout open. input input t13 r15 xtalout low low p16 n14 xtal32in 32.768 khz real time clock crystal oscillator pins. an external clock source can be connected to xtal32in leav ing xtal32out open. input input p15 m13 xtal32out output output p14 m12 clken external oscillator clock enable output low low 8 ma j6 j5 pgmclk programmable clock (14.7456 mhz max.) low low 8 ma k11 p14 ncs0 asynchronous memory chip select 0 high high 12 ma k10 p16 ncs1 asynchronous memory chip select 1 high high 12 ma p13 n15 ncs2 asynchronous memory chip select 2 high high 12 ma m12 n16 ncs3/ nmmspics asynchronous memory chip select 3 multimediacard spi mode chip select high: ncs3 high 12 ma table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 5 l12 l11 d0 data bus low low 12 ma m15 l13 d1 n13 l14 d2 l16 k11 d3 l15 l16 d4 l14 k14 d5 h11 j15 d6 k12 j12 d7 j15 j10 d8 j13 h16 d9 j10 h14 d10 h15 h11 d11 h13 g16 d12 g15 g9 d13 g11 g14 d14 g12 g12 d15 f15 f15 d16 f12 e15 d17 e14 d16 d18 d16 f12 d19 h10 e13 d20 d14 d14 d21 f10 e12 d22 a16 b16 d23 a14 d12 d24 b13 a16 d25 c13 b13 d26 e12 b14 d27 g10 c12 d28 b12 a14 d29 b11 b12 d30 d11 a12 d31 m16 m15 a0/nwe1 asynchronous address bus asynchronous memory write byte enable 1 high: nwe1 high 12 ma n14 m16 a1/nwe2 asynchronous address bus asynchronous memory write byte enable 2 high: nwe2 high 12 ma table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive
lh7a400 32-bit system-on-chip 6 12/8/03 preliminary data sheet m13 l15 a2/sa0 asynchronous address bus synchronous address bus low low 12 ma k16 k12 a3/sa1 low low 12 ma k15 k13 a4/sa2 low low 12 ma k14 k16 a5/sa3 low low 12 ma j8 j13 a6/sa4 low low 12 ma j16 j11 a7/sa5 low low 12 ma j14 j16 a8/sa6 low low 12 ma j9 h15 a9/sa7 low low 12 ma h16 h10 a10/sa8 low low 12 ma h14 h12 a11/sa9 low low 12 ma g16 g15 a12/sa10 low low 12 ma g14 g10 a13/sa11 low low 12 ma g13 g11 a14/sa12 low low 12 ma f16 f16 a15/sa13 low low 12 ma f14 e16 a16/sb0 asynchronous address bus synchronous device bank address 0 low low 12 ma e16 f13 a17/sb1 asynchronous address bus synchronous device bank address 1 low low 12 ma e13 e14 a18 asynchronous address bus low low 12 ma f11 d15 a19 d15 c16 a20 c16 c15 a21 b16 c14 a22 a15 b15 a23 a13 e11 a24 g8 d8 a25/scio asynchronous memory address bus smart card interface i/o (data) low: a25 low 12 ma f8 b7 a26/scclk asynchronous memory address bus smart card interface clock low: a26 low 12 ma a8 a7 a27/scrst asynchronous memory address bus smart card interface reset low: a27 low 12 ma d8 c8 noe asynchronous memory output enable high high 12 ma c8 f8 nwe0 asynchronous memory write byte enable 0 high high 12 ma d10 d9 nwe3 asynchronous memory write byte enable 3 high high 8 ma b10 e9 cs6/scke1_2 asynchronous memory chip select 6 synchronous memory clock enable 1 or 2 low: cs6 low 12 ma c10 a10 cs7/scke0 asynchronous memory chip select 7 synchronous memory clock enable 0 low: cs7 low 12 ma g9 a11 scke3 synchronous memory clock enable 3 low low 12 ma a10 b10 sclk synchronous memory clock low low 20 ma (sink) 12 ma (source) c14 c13 nscs0 synchronous memory chip select 0 high high 12 ma d13 a15 nscs1 synchronous memory chip select 1 high high 12 ma e11 d11 nscs2 synchronous memory chip select 2 high high 12 ma a12 e10 nscs3 synchronous memory chip select 3 high high 12 ma c12 a13 nswe synchronous memory write enable high high 12 ma c11 b11 ncas synchronous memory column address strobe signal high high 12 ma table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 7 f9 c11 nras synchronous memory row address strobe signal high high 12 ma a9 c9 dqm0 synchronous memory data mask 0 high high 12 ma b9 a9 dqm1 synchronous memory data mask 1 high high 12 ma d9 b9 dqm2 synchronous memory data mask 2 high high 12 ma e9 a8 dqm3 synchronous memory data mask 3 high high 12 ma j5 k1 pa0/lcdvd16 gpio port a lcd data bit 16. this clcdc output signal is always low. input: pa0 no change 8 ma k1 k2 pa1/lcdvd17 gpio port a lcd data bit 17. this clcdc output signal is always low. input: pa1 no change 8 ma k2 k3 pa2 gpio port a input no change 8 ma k3 k4 pa3 k5 k6 pa4 l1 k5 pa5 l2 l1 pa6 l3 l2 pa7 l4 l3 pb0/uartrx1 gpio port b uart1 receive data input input: pb0 no change 8 ma l5 m1 pb1/uarttx3 gpio port b uart3 transmit data out input: pb1 low if uart3 is enabled, otherwise no change 8 ma l7 m2 pb2/uartrx3 gpio port b uart3 receive data in input: pb2 no change 8 ma m2 m3 pb3/ uartcts3 gpio port b uart3 clear to send input: pb3 no change 8 ma m4 l5 pb4/ uartdcd3 gpio port b uart3 data carrier detect input: pb4 no change 8 ma n1 n1 pb5/ uartdsr3 gpio port b uart3 data set ready input: pb5 no change 8 ma n2 n2 pb6/swid/ smbd gpio port b single wire data smart battery data input: pb6 input if smb is enabled, otherwise no change 8 ma n3 m4 pb7/smbclk gpio port b smart battery clock input: pb7 input if smb is enabled, otherwise no change 8 ma p1 p1 pc0/uarttx1 gpio port c uart1 transmit data output low: pc0 no change 12 ma p2 p2 pc1/lcdps gpio port c hr-tft power save low: pc1 no change 12 ma r1 r1 pc2/ lcdvdden gpio port c hr-tft power sequence control low: pc2 no change 12 ma k6 m5 pc3/lcdrev gpio port c hr-tft gray scale voltage reverse low: pc3 no change 12 ma l8 p3 pc4/lcdsps gpio port c hr-tft reset row driver counter low: pc4 no change 12 ma t1 n4 pc5/lcdcls gpio port c hr-tft row driver clock low: pc5 no change 12 ma table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive
lh7a400 32-bit system-on-chip 8 12/8/03 preliminary data sheet t2 r2 pc6/lcdhrlp gpio port c lcd latch pulse low: pc6 no change 12 ma r2 n5 pc7/lcdspl gpio port c lcd start pulse left low: pc7 no change 12 ma m11 m9 pd0/lcdvd8 gpio port d lcd video data bus low: pd0 low if dual-panel lcd is enabled; otherwise, no change 12 ma l11 k10 pd1/lcdvd9 low: pd1 k8 p10 pd2/lcdvd10 low: pd2 n11 t11 pd3/lcdvd11 low: pd3 r9 t12 pd4/lcdvd12 low: pd4 t9 r11 pd5/lcdvd13 low: pd5 p10 r12 pd6/lcdvd14 low: pd6 r10 t13 pd7/lcdvd15 low: pd7 l10 t9 pe0/lcdvd4 gpio port e lcd video data bus input: pe0 low if 8-bit lcd is enabled, otherwise no change 12 ma n10 k9 pe1/lcdvd5 input: pe1 m9 t10 pe2/lcdvd6 input: pe2 m10 r10 pe3/lcdvd7 input: pe3 a6 a5 pf0/int0 gpio port f external fiq interrupt. interrupts can be level or edge triggered and are internally debounced. input: pf0 (schmitt) no change 8 ma b6 b4 pf1/int1 gpio port f external irq interrupts. interrupts can be level or edge triggered and are internally debounced. input: pf1 (schmitt) no change 8 ma c6 e7 pf2/int2 input: pf2 (schmitt) no change 8 ma h8 b3 pf3/int3 gpio port f external irq interrupt. interrupts can be level or edge triggered and are internally debounced. input: pf3 (schmitt) no change 8 ma b5 c5 pf4/int4/ scvccen gpio port f external irq interrupt. interrupts can be level or edge triggered and are internally debounced. smart card supply voltage enable input: pf4 (schmitt) low if sci is enabled; otherwise, no change 8 ma d6 d6 pf5/int5/ scdetect gpio port f external irq interrupt. interrupts can be level or edge triggered and are internally debounced. smart card detection input: pf5 (schmitt) no change 8 ma e6 a4 pf6/int6/ pcrdy1 gpio port f external irq interrupt. interrupts can be level or edge triggered and are internally debounced. ready for card 1 for pc card (pcmcia or compactflash) in single or dual card mode input: pf6 (schmitt) no change 8 ma c5 a3 pf7/int7/ pcrdy2 gpio port f external irq interrupt. interrupts can be level or edge triggered and are internally debounced. ready for card 2 for pc card (pcmcia or compactflash) in single or dual card mode input: pf7 (schmitt) no change 8 ma r3 m6 pg0/npcoe gpio port g output enable for pc card (pcmcia or compactflash) in single or dual card mode low: pg0 no change 8 ma t3 t1 pg1/npcwe gpio port g write enable for pc card (pcmcia or compactflash) in single or dual card mode low: pg1 no change 8 ma table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 9 l6 p4 pg2/npcior gpio port g i/o read strobe for pc card (pcmcia or compactflash) in single or dual card mode low: pg2 no change 8 ma m6 r3 pg3/npciow gpio port g i/o write strobe for pc card (pcmcia or compactflash) in single or dual card mode low: pg3 no change 8 ma n6 t2 pg4/npcreg gpio port g register memory access for pc card (pcmcia or compactflash) in single or dual card mode low: pg4 no change 8 ma m7 p5 pg5/npcce1 gpio port g card enable 1 for pc card (pcmcia or compactflash) in single or dual card mode. this signal and npcce2 are used by the pc card for decoding low and high byte accesses. low: pg5 no change 8 ma m8 r4 pg6/npcce2 gpio port g card enable 2 for pc card (pcmcia or compactflash) in single or dual card mode. this signal and npcce1 are used by the pc card for decoding low and high byte accesses. low: pg6 no change 8 ma n4 t3 pg7/pcdir gpio port g direction for pc card (pcmcia or compactflash) in single or dual card mode low: pg7 no change 8 ma p4 p6 ph0/ pcreset1 gpio port h reset card 1 for pc card (pcmcia or compactflash) in single or dual card mode input: ph0 no change 8 ma r4 t4 ph1/cfa8/ pcreset2 gpio port h address bit 8 for pc card (compactflash) in single card mode reset card 2 for pc card (pcmcia or compactflash) in dual card mode input: ph1 no change 8 ma t4 m7 ph2/ npcslote1 gpio port h enable card 1 for pc card (pcmcia or compactflash) in single or dual card mode. this signal is used for gating other control sig- nals to the appropriate pc card. input: ph2 no change 8 ma n7 t5 ph3/cfa9/ pcmciaa25/ npcslote2 gpio port h address bit 9 for pc card (compactflash) in single card mode address bit 25 for pc card (pcmcia) in single card mode enable card 2 for pc card (pcmcia or compactflash) in dual card mode. this signal is used for gating other control signals to the appropriate pc card. input: ph3 no change 8 ma p8 r6 ph4/ npcwait1 gpio port h wait signal for card 1 for pc card (pcmcia or compactflash) in single or dual card mode input: ph4 no change 8 ma p5 r7 ph5/cfa10/ pcmciaa24/ npcwait2 gpio port h address bit 10 for pc card (compactflash) in single card mode address bit 24 for pc card (pcmcia) in single card mode wait signal for card 2 for pc card (pcmcia or compactflash) in dual card mode input: ph5 no change 8 ma table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive
lh7a400 32-bit system-on-chip 10 12/8/03 preliminary data sheet r5 p7 ph6/ ac97reset gpio port h audio codec (ac97) reset input: ph6 no change 8 ma t5 t6 ph7/npc- statre gpio port h status read enable for pc card (pcmcia or compactflash) in single or dual card mode input: ph7 no change 8 ma r6 t7 lcdfp lcd frame synchronization pulse low low 12 ma r8 r9 lcdlp lcd line synchronization pulse low low 12 ma p9 p9 lcdenab/ lcdm lcd tft data enable lcd stn ac bias low: lcdenab low 12 ma n9 n9 lcddclk lcd data clock low low 12 ma p7 m8 lcdvd0 lcd video data bus low low 12 ma r7 p8 lcdvd1 t7 r8 lcdvd2 n8 t8 lcdvd3 t15 t16 usbdp usb data positive (differential pair) input input 75 ma (nom.) t16 r16 usbdn usb data negative (differential pair) input input 75 ma (nom.) e7 c7 npwme0 dc-dc converter pulse width modulator 0 enable input input d7 a6 npwme1 dc-dc converter pulse width modulator 1 enable input input c7 b6 pwm0 dc-dc converter pulse width modulator 0 output during normal operation and polarity selection input at reset input input 8 ma b7 b5 pwm1 dc-dc converter pulse width modulator 1 output during normal operation and polarity selection input at reset input input 8 ma c4 a2 acbitclk audio codec (ac97) clock audio codec (aci) clock input input d5 a1 acout audio codec (ac97) output audio codec (aci) output low low 8 ma b4 b2 acsync audio codec (ac97) synchronization audio codec (aci) synchronization low low 8 ma a4 e6 acin audio codec (ac97) input audio codec (aci) input input input a3 c3 mmcclk/ mmspiclk multimediacard clock (20 mhz max.) multimediacard spi mode clock low: mmcclk low 8 ma b3 b1 mmccmd/ mmspidin multimediacard command multimediacard spi mode data input input: mmccmd input 8 ma a2 d4 mmcdata/ mmspidout multimediacard data multimediacard spi mode data output input: mmcdata input 8 ma e2 e1 uartcts2 uart2 clear to send signal. this pin is an out- put for jtag boundary scan only. input input e3 f3 uartdcd2 uart2 data carrier detect signal. this pin is out- put for jtag boundary scan only. input input e5 g4 uartdsr2 uart2 data set ready signal input input f2 g5 uartirtx1 irda transmit low low 8 ma f3 g6 uartirrx1 irda receive. this pin is an output for jtag boundary scan only. input input f4 f1 uarttx2 uart2 transmit data output high high 8 ma table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 11 notes: *signals beginning with ?n? are active low. j7 g3 uartrx2 uart2 receive data input. this pin is an output for jtag boundary scan only. input input h4 j3 sspclk synchronous serial port clock low low 8 ma j1 j6 ssprx synchronous serial port receive input input j2 j7 ssptx synchronous serial port transmit low low 8 ma j3 j2 sspfrm/ nsspfrm synchronous serial port frame sync input: nsspfrm input 8 ma f6 g2 col0 keyboard interface high high 8 ma f5 g1 col1 g1 h3 col2 g2 h5 col3 g4 h6 col4 g5 h7 col5 h1 h2 col6 h2 h1 col7 h3 j1 tbuz timer buzzer (254 khz max.) low low 8 ma c3 f5 medchg boot device media change. used with the width0 and width1 pins to specify boot mem- ory device. input (schmitt) input p11 t14 width0 external memory width pins. also, used with medchg to specify the boot memory device size. input (schmitt) input r12 t15 width1 d1 e3 batok battery ok input (schmitt) input d2 f6 nbatchg battery change input (schmitt) input a1 e5 tdi jtag data in. this signal is internally pulled-up to vdd. input with pull-up input with pull-up b1 c2 tck jtag clock. this signal should be externally pulled-up to vdd. input input b2 d3 tdo jtag data out. this signal should be externally pulled up to vdd with a 33 k ? resistor. input no change 4 ma c1 c1 tms jtag test mode select. this signal is internally pulled-up to vdd. input with pull-up input with pull-up t12 p15 ntest0 test pin 0. internally pulled up to vdd. for normal mode, leave open. for jt ag mode, tie to gnd. see table 2. input with pull-up input with pull-up r15 p13 ntest1 test pin 1. internally pulled up to vdd. for normal and jtag mode, leave open. see table 2. input with pull-up input with pull-up table 1. functional pin list (cont?d) pbga pin cabga pin signal description reset state standby state output drive table 2. ntest pin function mode ntest0 ntest1 nureset jtag 0 1 1 normal 1 1 x
lh7a400 32-bit system-on-chip 12 12/8/03 preliminary data sheet notes: 1. the intensity bit is identical ly generated for all three colors. 2. mu = monochrome upper 3. cu = color upper 4. cl = color lower table 3. lcd data multiplexing pbga pin cabga pin lcd data signal stn tft ad-tft/ hr-tft mono 4-bit mono 8-bit color single panel dual panel single panel dual panel single panel dual panel k1 k2 lcdvd17 low j5 k1 lcdvd16 low r10 t13 lcdvd15 mlstn7 clstn7 intensity intensity p10 r12 lcdvd14 mlstn6 clstn6 blue4 blue4 t9 r11 lcdvd13 mlstn5 clstn5 blue3 blue3 r9 t12 lcdvd12 mlstn4 clstn4 blue2 blue2 n11 t11 lcdvd11 mlstn3 clstn3 blue1 blue1 k8 p10 lcdvd10 mlstn2 clstn2 blue0 blue0 l11 k10 lcdvd9 mlstn1 clstn1 green4 green4 m11 m9 lcdvd8 mlstn0 clstn0 green3 green3 m10 r10 lcdvd7 mlstn3 mustn7 mustn7 custn7 custn7 green2 green2 m9 t10 lcdvd6 mlstn2 mustn6 mustn6 custn6 custn6 green1 green1 n10 k9 lcdvd5 mlstn1 mustn5 mustn5 custn5 custn5 green0 green0 l10 t9 lcdvd4 mlstn0 mustn4 mustn4 custn4 custn4 red4 red4 n8 t8 lcdvd3 mustn3 mustn3 mustn3 mustn3 custn3 custn3 red3 red3 t7 r8 lcdvd2 mustn2 mustn2 mustn2 mustn2 custn2 custn2 red2 red2 r7 p8 lcdvd1 mustn1 mustn1 mustn1 mustn1 custn1 custn1 red1 red1 p7 m8 lcdvd0 mustn0 mustn0 mustn0 mustn0 custn0 custn0 red0 red0
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 13 table 4. 256-ball pbga package numerical pin list bga pin signal reset state standby state a1 tdi input with pull-up input with pull-up a2 mmcdata/mmspidout input: mmspidout low a3 mmcclk/mmspiclk low: mmspiclk low a4 acin input input a5 vss a6 pf0/int0 input: pf0 no change a7 vddc a8 a27/scrst low: a27 low a9 dqm0 high low a10 sclk low low a11 vss a12 nscs3 high high a13 a24 low low a14 d24 low low a15 a23 low low a16 d23 low low b1 tck input input b2 tdo input no change b3 mmccmd/mmspidin i nput: mmspidin low b4 acsync low low b5 pf4/int4/scvccen input: pf4 low if sci is enabled; otherwise, no change b6 pf1/int1 input: pf1 no change b7 pwm1 input input b8 vdd b9 dqm1 high low b10 cs6/scke1_2 low: cs6 low b11 d30 low low b12 d29 low low b13 d25 low low b14 vdd b15 vssc b16 a22 low low c1 tms input with pull-up input with pull-up c2 nextpwr input input c3 medchg input input c4 acbitclk input input c5 pf7/int7/pcrdy2 input: pf7 no change c6 pf2/int2 pf2/int2 no change c7 pwm0 input input c8 nwe0 high high c9 vssc c10 cs7/scke0 low: cs7 low c11 ncas high high c12 nswe high high c13 d26 low low
lh7a400 32-bit system-on-chip 14 12/8/03 preliminary data sheet c14 nscs0 high high c15 vss c16 a21 low low d1 batok input input d2 nbatchg input input d3 npor input input d4 wakeup input input d5 acout low low d6 pf5/int5/scdetect input: pf5 no change d7 npwme1 input input d8 noe high high d9 dqm2 high low d10 nwe3 high high d11 d31 low low d12 vddc d13 nscs1 high high d14 d21 low low d15 a20 low low d16 d19 low low e1 vddc e2 uartcts2 input input e3 uartdcd2 input input e4 npwrfl input input e5 uartdsr2 input input e6 pf6/int6/pcrdy1 input: pf6 no change e7 npwme0 input input e8 vss e9 dqm3 high low e10 vdd e11 nscs2 high high e12 d27 low low e13 a18 low low e14 d18 low low e15 vddc e16 a17/sb1 low: sbank1 low f1 vdd f2 uartirtx1 low low f3 uartirrx1 input input f4 uarttx2 high high f5 col1 high high f6 col0 high high f7 vss f8 a26/scclk low: a26 low f9 nras high high f10 d22 low low table 4. 256-ball pbga package numerical pin list (cont?d) bga pin signal reset state standby state
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 15 f11 a19 low low f12 d17 low low f13 vdd f14 a16/sb0 low: sbank0 low f15 d16 low low f16 a15/sa13 low: sa13 low g1 col2 high high g2 col3 high high g3 vss g4 col4 high high g5 col5 high high g6 vssc g7 vdd g8 a25/scio low: a25 low g9 scke3 low low g10 d28 low low g11 d14 low low g12 d15 low low g13 a14/sa12 low: sa12 low g14 a13/sa11 low: sa11 low g15 d13 low low g16 a12/sa10 low: sa10 low h1 col6 high high h2 col7 high high h3 tbuz low low h4 sspclk low low h5 vssc h6 nureset input input h7 vss h8 pf3/int3 input: pf3 no change h9 vss h10 d20 low low h11 d6 low low h12 vssc h13 d12 low low h14 a11/sa9 low: sa9 low h15 d11 low low h16 a10/sa8 low: sa8 low j1 ssprx input input j2 ssptx low low j3 sspfrm/nsspfrm input: nsspfrm input j4 vddc j5 pa0/lcdvd16 input: pa0 no change j6 pgmclk low low j7 uartrx2 input input table 4. 256-ball pbga package numerical pin list (cont?d) bga pin signal reset state standby state
lh7a400 32-bit system-on-chip 16 12/8/03 preliminary data sheet j8 a6/sa4 low: sa4 low j9 a9/sa7 low: sa7 low j10 d10 low low j11 vdd j12 vdd j13 d9 low low j14 a8/sa6 low: sa6 low j15 d8 low low j16 a7/sa5 low: sa5 low k1 pa1/lcdvd17 input: pa1 no change k2 pa2 input no change k3 pa3 input no change k4 vss k5 pa4 input no change k6 pc3/lcdrev low: pc3 no change k7 vdd k8 pd2/lcdvd10 low: pd2 low if dual-panel lcd is enabled; otherwise, no change k9 vddc k10 ncs1 high high k11 ncs0 high high k12 d7 low low k13 vss k14 a5/sa3 low: sa3 low k15 a4/sa2 low: sa2 low k16 a3/sa1 low: sa1 low l1 pa5 input no change l2 pa6 input no change l3 pa7 input no change l4 pb0/uartrx1 input: pb0 no change l5 pb1/uarttx3 input: pb1 low if uart3 is enabled, otherwise no change l6 pg2/npcior low: pg2 no change l7 pb2/uartrx3 input: pb2 no change l8 pc4/lcdsps low: pc4 no change l9 vssc l10 pe0/lcdvd4 input: pe0 low if 8-bit lcd is enabled, otherwise no change l11 pd1/lcdvd9 low: pd1 low if dual-panel lcd is enabled; otherwise, no change l12 d0 low low l13 vddc l14 d5 low low l15 d4 low low l16 d3 low low m1 vdd m2 pb3/uartcts3 input: pb3 no change m3 vssc table 4. 256-ball pbga package numerical pin list (cont?d) bga pin signal reset state standby state
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 17 m4 pb4/uartdcd3 input: pb4 no change m5 vdd m6 pg3/npciow low: pg3 no change m7 pg5/npcce1 low: pg5 no change m8 pg6/npcce2 low: pg6 no change m9 pe2/lcdvd6 input: pe2 low if 8-bit lcd is enabled; otherwise no change m10 pe3/lcdvd7 input: pe3 low if 8-bit lcd is enabled; otherwise no change m11 pd0/lcdvd8 low: pd0 low if dual-panel lcd is enabled; otherwise, no change m12 ncs3/nmmspics high: ncs3 high m13 a2/sa0 low: sa0 low m14 vdd m15 d1 low low m16 a0/nwe1 high: nwe1 high n1 pb5/uartdsr3 input: pb5 no change n2 pb6/swid/smbd input: pb6 input if sm b is enabled; otherwise no change n3 pb7/smbclk input: pb7 input if smb is enabled; otherwise no change n4 pg7/pcdir low: pg7 no change n5 vss n6 pg4/npcreg low: pg4 no change n7 ph3/cfa9/pcmciaa25/npcs lote2 input: ph3 no change n8 lcdvd3 low low n9 lcddclk low low n10 pe1/lcdvd5 input: pe1 low if 8-bit lcd is enabled; otherwise no change n11 pd3/lcdvd11 low: pd3 low if dual-panel lcd is enabled; otherwise, no change n12 vdda n13 d2 low low n14 a1/nwe2 high: nwe2 high n15 vssc n16 vss p1 pc0/uarttx1 low: pc0 no change p2 pc1/lcdps low: pc1 no change p3 vddc p4 ph0/pcreset1 input: ph0 no change p5 ph5/cfa10/pcmciaa24/npcwait2 input: ph5 no change p6 vss p7 lcdvd0 low low p8 ph4/npcwait1 input: ph4 no change p9 lcdenab/lcdm low: lcdenab low p10 pd6/lcdvd14 low: pd6 low if dual-panel lcd is enabled; otherwise, no change p11 width0 input input p12 vssa p13 ncs2 high high p14 clken low low table 4. 256-ball pbga package numerical pin list (cont?d) bga pin signal reset state standby state
lh7a400 32-bit system-on-chip 18 12/8/03 preliminary data sheet note: ?no change? means the pin remains as it was programmed prior to entering the standby state. p15 xtal32out output output p16 xtal32in input input r1 pc2/lcdvdden low: pc2 no change r2 pc7/lcdspl low: pc7 no change r3 pg0/npcoe low: pg0 no change r4 ph1/cfa8/pcreset2 i nput: ph1 no change r5 ph6/nac97reset input: ph6 no change r6 lcdfp low low r7 lcdvd1 low low r8 lcdlp low low r9 pd4/lcdvd12 low: pd4 low if dual-panel lcd is enabled; otherwise, no change r10 pd7/lcdvd15 low: pd7 low if dual-panel lcd is enabled; otherwise, no change r11 vdda r12 width1 input input r13 xtalin input input r14 vdd r15 ntest1 input with pull-up input with pull-up r16 vss t1 pc5/lcdcls low: pc5 no change t2 pc6/lcdhrlp low: pc6 no change t3 pg1/npcwe low: pg1 no change t4 ph2/npcslote1 input: ph2 no change t5 ph7/npcstatre input: ph7 no change t6 vdd t7 lcdvd2 low low t8 vddc t9 pd5/lcdvd13 low: pd5 low if dual-panel lcd is enabled; otherwise, no change t10 vssc t11 vssa t12 ntest0 input with pu ll-up input with pull-up t13 xtalout low low t14 vss t15 usbdp high high t16 usbdn low low table 4. 256-ball pbga package numerical pin list (cont?d) bga pin signal reset state standby state
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 19 table 5. 256-ball cabga package numerical pin list cabga pin signal reset state standby state a1 acout low low a2 acbitclk input input a3 pf7/int7/pcrdy2 input: pf7 (schmitt) no change a4 pf6/int6/pcrdy1 input: pf6 (schmitt) no change a5 pf0/int0 input: pf0 (schmitt) no change a6 npwme1 input input a7 a27/scrst low: a27 low a8 dqm3 high high a9 dqm1 high high a10 cs7/scke0 low: cs7 low a11 scke3 low low a12 d31 low low a13 nswe high high a14 d29 low low a15 nscs1 high high a16 d25 low low b1 mmccmd/mmspidin i nput: mmccmd input b2 acsync low low b3 pf3/int3 input: pf3 (schmitt) no change b4 pf1/int1 input: pf1 (schmitt) no change b5 pwm1 input input b6 pwm0 input input b7 a26/scclk low: a26 low b8 vss b9 dqm2 high high b10 sclk low low b11 ncas high high b12 d30 low low b13 d26 low low b14 d27 low low b15 a23 low low b16 d23 low low c1 tms input with pull- up input with pull-up c2 tck input input c3 mmcclk/mmspiclk low: mmcclk low c4 vddc c5 pf4/int4/scvccen input: pf4 (schmitt) low if sci is enabled; otherwise, no change c6 vss c7 npwme0 input input c8 noe high high c9 dqm0 high high c10 vdd c11 nras high high
lh7a400 32-bit system-on-chip 20 12/8/03 preliminary data sheet c12 d28 low low c13 nscs0 high high c14 a22 low low c15 a21 low low c16 a20 low low d1 nureset input (schmitt) input d2 nextpwr input (schmitt) input d3 tdo input no change d4 mmcdata/mmspidout input: mmcdata input d5 vss d6 pf5/int5/scdetect input: pf5 (schmitt) no change d7 vddc d8 a25/scio low: a25 low d9 nwe3 high high d10 vddc d11 nscs2 high high d12 d24 low low d13 vss d14 d21 low low d15 a19 low low d16 d18 low low e1 uartcts2 input input e2 wakeup input (schmitt) input e3 batok input (schmitt) input e4 npor input input e5 tdi input with pull-up input with pull-up e6 acin input input e7 pf2/int2 input: pf2 (schmitt) no change e8 vss e9 cs6/scke1_2 low: cs6 low e10 nscs3 high high e11 a24 low low e12 d22 low low e13 d20 low low e14 a18 low low e15 d17 low low e16 a16/sb0 low low f1 uarttx2 high high f2 npwrfl input (schmitt) input f3 uartdcd2 input input f4 vddc f5 medchg input (schmitt) input f6 nbatchg input (schmitt) input table 5. 256-ball cabga package numerical pin list cabga pin signal reset state standby state
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 21 f7 vss f8 nwe0 high high f9 vdd f10 vddc f11 vdd f12 d19 low low f13 a17/sb1 low low f14 vdd f15 d16 low low f16 a15/sa13 low low g1 col1 high high g2 col0 high high g3 uartrx2 input input e5 uartdsr2 input input g5 uartirtx1 low low g6 uartirrx1 input input g7 vssc g8 vdd g9 d13 low low g10 a13/sa11 low low g11 a14/sa12 low low g12 d15 low low g13 vss g14 d14 low low g15 a12/sa10 low low g16 d12 low low h1 col7 high high h2 col6 high high h3 col2 high high h4 vssc h5 col3 high high h6 col4 high high h7 col5 high high h8 vssc h9 vss h10 a10/sa8 low low h11 d11 low low h12 a11/sa9 low low h13 vdd h14 d10 low low h15 a9/sa7 low low h16 d9 low low j1 tbuz low low table 5. 256-ball cabga package numerical pin list cabga pin signal reset state standby state
lh7a400 32-bit system-on-chip 22 12/8/03 preliminary data sheet j2 sspfrm/nsspfrm input: nsspfrm input j3 sspclk low low j4 vddc j5 pgmclk low low j6 ssprx input input j7 ssptx low low j8 vddc j9 vdd j10 d8 low low j11 a7/sa5 low low j12 d7 low low j13 a6/sa4 low low j14 vss j15 d6 low low j16 a8/sa6 low low k1 pa0/lcdvd16 input: pa0 no change k2 pa1/lcdvd17 input: pa1 no change k3 pa2 input no change k4 pa3 input no change k5 pa5 input no change k6 pa4 input no change k7 vss k8 vddc k9 pe1/lcdvd5 input: pe1 k10 pd1/lcdvd9 low: pd1 k11 d3 low low k12 a3/sa1 low low k13 a4/sa2 low low k14 d5 low low k15 vdd k16 a5/sa3 low low l1 pa6 input no change l2 pa7 input no change l3 pb0/uartrx1 input: pb0 no change l4 vssc l5 pb4/uartdcd3 input: pb4 no change l6 vddc l7 vdd l8 vss l9 vssc l10 vss l11 d0 low low l12 vss table 5. 256-ball cabga package numerical pin list cabga pin signal reset state standby state
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 23 l13 d1 low low l14 d2 low low l15 a2/sa0 low low l16 d4 low low m1 pb1/uarttx3 input: pb1 low if uart3 is enabled, otherwise no change m2 pb2/uartrx3 input: pb2 no change m3 pb3/uartcts3 input: pb3 no change m4 pb7/smbclk input: pb7 input if smb is enabled, otherwise no change m5 pc3/lcdrev low: pc3 no change m6 pg0/npcoe low: pg0 no change m7 ph2/npcslote1 input: ph2 no change m8 lcdvd0 low low m9 pd0/lcdvd8 low: pd0 low if dual-panel lcd is enabled; otherwise, no change m10 vdda m11 vss m12 clken low low m13 xtal32out output output m14 vss m15 a0/nwe1 high: nwe1 high m16 a1/nwe2 high: nwe2 high n1 pb5/uartdsr3 input: pb5 no change n2 pb6/swid/smbd input: pb6 input if sm b is enabled, otherwise no change n3 vssc n4 pc5/lcdcls low: pc5 no change n5 pc7/lcdspl low: pc7 no change n6 vdd n7 vssc n8 vdd n9 lcddclk low low n10 vssc n11 vssa n12 vdd n13 vdd n14 xtal32in input input n15 ncs2 high high n16 ncs3/nmmspics high: ncs3 high p1 pc0/uarttx1 low: pc0 no change p2 pc1/lcdps low: pc1 no change p3 pc4/lcdsps low: pc4 no change p4 pg2/npcior low: pg2 no change p5 pg5/npcce1 low: pg5 no change p6 ph0/pcreset1 input: ph0 no change table 5. 256-ball cabga package numerical pin list cabga pin signal reset state standby state
lh7a400 32-bit system-on-chip 24 12/8/03 preliminary data sheet p7 ph6/ac97reset input: ph6 no change p8 lcdvd1 low low p9 lcdenab/lcdm low: lcdenab low p10 pd2/lcdvd10 low: pd2 no change p11 vdd no change p12 vdda p13 ntest1 input with pu ll-up input with pull-up p14 ncs0 high high p15 ntest0 input with pu ll-up input with pull-up p16 ncs1 high high r1 pc2/lcdvdden low: pc2 no change r2 pc6/lcdhrlp low: pc6 no change r3 pg3/npciow low: pg3 no change r4 pg6/npcce2 low: pg6 no change r5 vssc r6 ph4/npcwait1 input: ph4 no change r7 ph5/cfa10/pcmciaa24/npcwait2 input: ph5 no change r8 lcdvd2 low low r9 lcdlp low low r10 pe3/lcdvd7 input: pe3 no change r11 pd5/lcdvd13 low: pd5 no change r12 pd6/lcdvd14 low: pd6 no change r13 vssa r14 xtalin input input r15 xtalout low low r16 usbdn input input t1 pg1/npcwe low: pg1 no change t2 pg4/npcreg low: pg4 no change t3 pg7/pcdir low: pg7 no change t4 ph1/cfa8/pcreset2 input: ph1 no change t5 ph3/cfa9/pcmciaa25/npcs lote2 input: ph3 no change t6 ph7/npcstatre input: ph7 no change t7 lcdfp low low t8 lcdvd3 low low t9 pe0/lcdvd4 input: pe0 low if 8-bit lcd is enabled, otherwise no change t10 pe2/lcdvd6 input: pe2 no change t11 pd3/lcdvd11 low: pd3 no change t12 pd4/lcdvd12 low: pd4 no change t13 pd7/lcdvd15 low: pd7 no change t14 width0 input (schmitt) input t15 width1 input (schmitt) input t16 usbdp input input table 5. 256-ball cabga package numerical pin list cabga pin signal reset state standby state
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 25 system descriptions arm922t processor the lh7a400 microcontroller features the arm922t cached core with an advanced high perfor- mance bus (ahb) interface. the processor is a mem- ber of the arm9t family of processors. for more information, see the arm document, ?arm922t tech- nical reference manual?, available on arm?s website at www.arm.com. clock and state controller the clocking scheme in the lh7a400 is based around two primary oscillator inputs. these are the 14.7456 mhz input crystal and the 32.768 khz real time clock oscillator. see figure 3. the 14.7456 mhz oscil- lator is used to generate the main system clock domains for the lh7a400, where as the 32.768 khz is used for controlling the po wer down operations and real time clock peripheral. the clock and state control- ler provides the clock gating and frequency division necessary, and then supplies the clocks to the proces- sor and to the rest of the system. the amount of clock gating that actually takes place is dependent on the current power saving mode selected. the 32.768 khz clock provides the source for the real time clock tree and powe r-down logic.this clock is used for the power state control in the design and is the only clock in the lh7a400 that runs permanently. the 32.768 khz clock is divided down to 1 hz using a ripple divider to save power. this generated 1 hz clock is used in the real time clock counter. the 14.7456 mhz source is used to generate the main system clocks for the lh7a400. it is the source for pll1 and pll2, it acts as the primary clock to the peripherals and is the source clock to the programma- ble clock (pgm) divider. pll1 provides the main clock tree for the chip, it generates the following clocks: fclk, hclk and pclk. fclk is the clock that drives the arm922t core. hclk is the main bus (ahb) clock, as such it clocks all memory interfaces, bus arbitrators and the ahb peripherals. hclk is generated by dividing fclk by 1, 2, 3, or 4. hclk can be gated by the system to enable low power operation. pclk is the peripheral bus (apb) clock. it is generated by dividing hclk by either 2, 4, or 8. pll2 is used to generate a fixed frequency of 48 mhz for the usb peripheral. figure 2. application diagram codec battery dc to dc voltage generation circuitry multimedia card touch screen contr. mmc sci pcmcia compact flash uart usb sdram sram rom flash dma ac97 stn/tft/ ad-tft ir gpio ssp uart lh7a400 pc card lh7a400-3 1 2 3 4 5 6 7 8 9 * 0 # bmi smart card
lh7a400 32-bit system-on-chip 26 12/8/03 preliminary data sheet power modes the lh7a400 has three operational states: run, halt, and standby. in run mode, all clocks are hard- ware-enabled and the processor is clocked. halt mode stops the processor clock while waiting for an event such as a key press, but the device continues to func- tion. finally, standby equates to the computer being switched ?off?, i.e. no display (lcd disabled) and the main oscillator is shut down . the 32.768 khz oscillator operates in all three modes. reset modes there are three external signals that can generate resets to the lh7a400; these are npor (power on reset), npwrfl (power fa ilure) and nureset (user reset). if any of these are active, a system reset is gen- erated internally. a npor reset performs a full system reset. the npwrfl and nureset resets will perform a full system reset except for the sdram refresh con- trol, sdram global config uration, sdram device configuration and the rtc peripheral registers. the sdram controller will issue a self-refresh command to external sdram before the system enters this reset (the npwrfl and nureset resets only, not so for the npor reset). this allows th e system to maintain its real time clock and sdram contents. on coming out of reset, the chip enters standby mode. once in run mode the pwrsr register can be interrogated to deter- mine the nature of the reset, and the trigger source, after which software can then take appropriate actions. data paths the data paths in the lh7a400 are: the amba ahb bus the amba apb bus the external bus interface the lcd ahb bus the dma busses. amba ahb bus the advanced microprocessor bus architecture advanced high-performance bus (amba ahb) bus is a high speed 32-bit-wide data bus. the amba ahb is for high-performance, high clock frequency system modules. peripherals that have high bandwidth requirements are connected to the lh7a400 core processor using the ahb bus. these include the external and internal memory interfaces, the lcd registers, palette ram and the bridge to the advanced peripheral bus (apb) interface. the apb bridge tr ansparently converts the ahb access into the slow er speed apb accesses. all of the control registers for the apb peripherals are pro- grammed using the ahb - apb bridge interface. the main ahb data and address lines are configured using a multiplexed bus. this removes the need for tri-state buffers and bus holders, and simplifies bus arbitration. figure 3. clock and state controller block diagram 14.7456 mhz main osc. hclk 32.768 khz rtc osc. /2, /4, /8 pclks fclk hclk (to processor core) lh7a400-4 state controller divide register
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 27 amba apb bus the amba apb bus is a lower-speed 32-bit-wide peripheral data bus. the speed of this bus is selectable to be a divide-by-2, divide-by-4 or divide-by-8 of the speed of the ahb bus. external bus interface the external bus interface (ebi) provides a 32-bit wide, high speed gateway to external memory devices. the memory devices supported include: asynchronous ram/rom/flash synchronous dram/flash pcmcia interfaces compactflash interfaces. the ebi can be controlled by either the asynchro- nous memory controller or synchronous memory con- troller. there is an arbiter on the ebi input, with priority given to the synchronous memory controller interface. lcd ahb bus the lcd controller has its own local memory bus that connects it to the system?s embedded memory and external sdram. the function of this local data bus is to allow the lcd controller to perform its video refresh function without congesting the ahb bus. this leads to better system performance and lower power consump- tion. there is an arbiter on both the embedded memory and the synchronous memory controller. in both cases the lcd bus is given priority. dma buses the lh7a400 has a dma system that connects the higher speed/higher data volume apb peripherals (mmc, usb and ac97) to the ahb bus. this enables the efficient transfer of data between these peripherals and external memory without the intervention of the arm922t core. the dma engine does not support memory to memory transfers. memory map the lh7a400 system has a 32-bit-wide address bus. this allows it to address up to 4gb of memory. this memory space is subdivided into a number of memory banks; see figure 4. four of these banks (each of 256mb) are allocated to the synchronous memory con- troller. eight of the banks (again, each 256mb) are allo- cated to the asynchronous memory controller. two of these eight banks are designed for pcmcia systems. part of the remaining memory space is allocated to the embedded sram, and to the control registers of the ahb and apb. the rest is unused. the lh7a400 can boot from either synchronous or asynchronous rom/flash. the selection is determined by the value of the medchg pin at power on reset as shown in table 6. when booting from synchronous memory, then synchronous bank 4 (nscs3) is mapped into memory location zero. when booting from asyn- chronous memory, asynchronous memory bank 0 (nscs0) is mapped into memory location zero. figure 4 shows the memory map of the lh7a400 system for the two boot modes. once the lh7a400 has booted, the boot code can configure the arm922t mmu to remap the low mem- ory space to a location in ra m. this allows the user to set the interrupt vector table. interrupt controller the lh7a400 interrupt controller is designed to con- trol the interrupts from 28 different sources. four inter- rupt sources are mapped to the fiq input of the arm922t and 24 are mapped to the irq input. fiqs have a higher priority than the irqs. if two interrupts with the same priority become active at the same time, the priority must be resolved in software. when an interrupt becomes active, the interrupt con- troller generates an fiq or irq if the corresponding mask bit is set. no latching of interrupts takes place in the controller. after a power on reset all mask register bits are cleared, therefore masking all interrupts. hence, enabling of the mask register must be done by software after a power-on-reset. table 6. boot modes boot mode latched boot- width1 latched boot- width0 latched medchg 8-bit rom 0 0 0 16-bit rom 0 1 0 32-bit rom 1 0 0 32-bit rom 1 1 0 16-bit sflash (initializes mode register) 0 0 1 16-bit srom (initializes mode register) 0 1 1 32-bit sflash (initializes mode register) 1 0 1 32-bit srom (initializes mode register) 1 1 1
lh7a400 32-bit system-on-chip 28 12/8/03 preliminary data sheet external bus interface the external bus interface allows the arm922t, lcd controller and dma engine access to an external memory system. the lcd co ntroller has access to an internal frame buffer in embedded sram and an exten- sion buffer in synchronous memory for large displays. the processor and dma engine share the main system bus, providing access to al l external memory devices and the embedded sram frame buffer. an arbitration unit ensures that control over the external bus interface (ebi) is only granted when an existing access has been completed. see figure 5. embedded sram the amount of embedded sram contained in the lh7a400 is 80kb. this embedded memory is designed to be used for storing code, data, or lcd frame data and to be contiguous with external sdram. the 80kb is large enough to store a qvga panel (320 240) at 8 bits per pixel, equivalent to 70kb of information. containing the frame buffer on chip reduces the overall power consumed in any application that uses the lh7a400. normally, the system has to perform external accesses to acquire this data. the lcd con- troller is designed to automatically use an overflow frame buffer in sdram if a larger screen size is required. this overflow buffer can be located on any 4kb page boundary in sdram, allowing software to set the mmu (in the lcd controller) page tables such that the two memory areas appear contiguous. byte, half-word and word accesses are permissible. asynchronous memory controller the asynchronous memory controller is incorpo- rated as part of the memory controller to provide an interface between the amba ahb system bus and external (off-chip) memory devices. the asynchronous memory controller provides sup- port for up to eight independently configurable memory banks simultaneously. each memory bank is capable of supporting: sram rom flash eprom burst rom memory. each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. the memory controller can be configured to support either little- endian or big-endian operation. the memory banks can be configured to support: non-burst read and write accesses only to high- speed cmos static ram. non-burst write accesses , nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. figure 4. memory mapping for each boot mode asynchronous memory (ncs0) f000.0000 synchronous memory (nscs2) synchronous memory (nscs1) d000.0000 synchronous memory (nscs0) reserved b001.4000 embedded sram reserved 8000.3800 e000.0000 c000.0000 ahb internal registers apb internal registers 8000.0000 asynchronous memory (cs7) asynchronous memory (cs6) 6000.0000 pcmcia/compactflash (npcslote2) pcmcia/compactflash (npcslote1) 4000.0000 asynchronous memory (ncs3) asynchronous memory (ncs2) 2000.0000 7000.0000 5000.0000 b000.0000 8000.2000 3000.0000 1000.0000 asynchronous memory (ncs1) synchronous rom (nscs3) 0000.0000 synchronous memory boot synchronous memory (nscs3) synchronous memory (nscs2) synchronous memory (nscs1) synchronous memory (nscs0) reserved embedded sram reserved ahb internal registers apb internal registers asynchronous memory (cs7) asynchronous memory (cs6) pcmcia/compactflash (npcslote2) pcmcia/compactflash (npcslote1) asynchronous memory (ncs3) asynchronous memory (ncs2) asynchronous memory (ncs1) asynchronous rom (ncs0) 256mb 256mb 256mb 256mb 256mb 256mb 256mb 256mb 256mb 80kb 256mb 256mb 256mb asynchronous memory boot lh7a400-6
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 29 figure 5. external bus interface block diagram lh7a400-8 synchronous dynamic memory controller (sdmc) pcmcia/cf support arbiter color lcd controller (clcdc) 80kb embedded sram lcd ahb asynchronous static memory controller (smc) external bus interface (ebi) sdram data address and control sdram arm922t lcd memory management unit (mmu) dma controller ad-tft lcd timing controller sram rom advanced high-performance bus (ahb) arbiter arbiter arbiter internal to the lh7a400 external to the lh7a400
lh7a400 32-bit system-on-chip 30 12/8/03 preliminary data sheet the asynchronous memory controller has six main functions: memory bank select access sequencing wait states generation byte lane write control external bus interface compactflash or pcmcia interfacing. synchronous memory controller the synchronous memory co ntroller provides a high speed memory interface to a wide variety of synchro- nous memory devices, including sdram, synchro- nous flash and sy nchronous roms. the key features of the controller are: lcd dma port for high bandwidth up to four synchronous memory banks that can be independently set up special configuration bits for synchronous rom operation ability to program synchr onous flash devices using write and erase commands on booting from synchronous rom, (and optionally with synchronous flash), a configuration sequence is performed before releasing the processor from reset data is transferred between the controller and the sdram in quad-word bursts. longer transfers within the same page are concatenated, forming a seam- less burst programmable for 16- or 32-bit data bus size two reset domains are provided to enable sdram contents to be preserved over a ?soft? reset power saving synchronous memory scke and external clock modes provided. multimediacard (mmc) the mmc adapter combines all of the requirements and functions of an mmc host. the adapter supports the full mmc bus protocol, defined by the mmc defini- tion group?s specification v.2.11. the controller can also implement the spi interface to the cards. interface description and mmc overview the mmc controller uses the three-wire serial data bus (clock, command, and data) to transfer data to and from the mmc card, and to configure and acquire status information from the card?s registers. mmc bus lines can be divided into three groups: power supply: vdd and vss data transfer: mmccmd, mmcdata clock: mmclk. multimediacard adapter the multimediacard adapter implements multimedia- card specific functions, serves as the bus master for the multimediacard bus and implements the standard inter- face to the multimediacard cards (card initialization, crc generation and validation, command/response transactions, etc.). smart card interface (sci) the sci (iso7816) interfaces to an external smart card reader. the sci can autonomously control data transfer to and from the smart card. transmit and receive data fifos are provided to reduce the required interaction between the cpu core and the peripheral. sci features supports asynchronous t0 and t1 transmission protocols supports clock rate conversion factor f = 372, with bit rate adjustment factors d = 1, 2, or 4 supported eight-character-deep buffered tx and rx paths direct interrupts for tx and rx fifo level monitoring interrupt status register hardware-initiated card deactivation sequence on detection of card removal software-initiated card deactivation sequence on transaction complete limited support for synchronous smart cards via registered input/output. programmable parameters smart card clock frequency communication baud rate protocol convention card activation/deactivation time check for maximum time for first character of answer to reset - atr reception check for maximum duration of atr character stream check for maximum time of receipt of first character of data stream check for maximum time allowed between characters character guard time block guard time transmit/receive character retry.
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 31 direct memory acce ss controller (dma) the dma controller interfac es streams from the fol- lowing three peripherals to the system memory: usb (1 tx and 1 rx dma channel) mmc (1 tx and 1 rx dma channel) ac97 (3 tx and 3 rx dma channels). each has its own bi-directional peripheral dma bus capable of transferring data in both directions simulta- neously. all memory transfers take place via the main system ahb bus. dma specific features are: independent dma channels for tx and rx two buffer descriptors per channel to avoid poten- tial data under/over-flows due to software introduced latency no buffer wrapping buffer size may be equal to, greater than or less than the packet size. transfers can automatically switch between buffers. maskable interrupt generation internal arbitration between dma channels and external bus arbiter. for dma data transfer sizes, byte, word and quad- word data transfers are supported. a set of control and status registers are available to the system processor for se tting up dma operations and monitoring their status. a system interrupt is gen- erated when any or all of the dma channels wish to inform the processor that a new buffer needs to be allo- cated. the dma controller services three peripherals using ten dma channels, each with its own peripheral dma bus capable of transferring data in both directions simultaneously. the mmc and usb peripherals each use two dma channels, one for transmit and one for receive. the ac97 peripheral uses six dma channels (three trans- mit and three receive) to allow different sample fre- quency data queues to be handled with low software overheads. the dma controller does not support memory to memory transfers. usb device the features of the usb are: fully compliant to usb 1.1 specification provides a high level interf ace that shields the firm- ware from usb protocol details compatible with both openhci and intel?s uhci standards supports full-speed (12 mbps) functions supports suspend and resume signalling. color lcd controller the lh7a400?s lcd controller is programmable to support up to 1,024 768, 16-bit color lcd panels. it interfaces directly to st n, color stn, tft, ad-tft, and hr-tft panels. unlike ot her lcd controllers, the lh7a400?s lcd controller incorporates the timing con- version logic from tft to hr-tft, allowing a direct interface to hr-tft and minimi zing external chip count. the color lcd controller features support for: up to 1,024 768 resolution 16-bit video bus stn, color stn, ad-tft, hr-tft, tft panels single and dual scan stn panels up to 15 gray shades up to 64,000 colors ac97 advanced audio codec interface the ac97 advanced audi o codec controller includes a 5-pin serial interface to an external audio codec. the ac97 link is a bi-directional, fixed rate, serial pulse code modulation (pcm) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. the ac97 controller contains logic that controls the ac97 link to the audio codec and an interface to the amba apb. its main features include: serial-to-parallel conversi on for data received from the external codec parallel-to-serial conversion for data transmitted to the external codec reception/transmission of control and status infor- mation via the amba apb interface supports up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. the transmit and receive paths are buffered with internal fifo memories, allowing data to be stored indepen- dently in both transmit and receive modes. the out- going data for the fifos can be written via either the apb interface or with dma channels 1 - 3.
lh7a400 32-bit system-on-chip 32 12/8/03 preliminary data sheet audio codec in terface (aci) the aci provides: a digital serial interface to an off-chip 8-bit codec all the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to or from the codec device. the interface supports full duplex operation and the transmit and receive paths are buffered with internal fifo memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. the aci includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip aci clock input (aciclk). transmit data values are output synchronous with the rising edge of the bit clock output. receive data values are sampled on the falling edge of the bit clock output. the start of a data frame is indicated by a synchroniza- tion output signal that is synchronous with the bit clock. synchronous serial port (ssp) the lh7a400 ssp is a master-only interface for synchronous serial communication with device periph- eral devices that has either motorola spi, national semiconductor microwire or texas instruments synchronous serial interfaces. the lh7a400 ssp performs serial-to-parallel con- version on data received from a peripheral device. the transmit and receive paths are buffered with internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. serial data is transmitted on ssptxd and received on ssprxd. the lh7a400 ssp includes a programmable bit rate clock divider and prescaler to generate the serial output clock sclk from the input clock sspclk. bit rates are supported to 2 mhz and beyond, subject to choice of frequency for sspclk; the maximum bit rate will usu- ally be determined by peripheral devices. uart/irda the lh7a400 contains three uarts, uart1, uart2, and uart3. the uart performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion on data transmitted to the peripheral device. the transmit and receive paths are buffered with inter- nal fifo memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. the uart can generate: four individually maskab le interrupts from the receive, transmit and modem status logic blocks a single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. if a framing, parity or break error occurs during reception, the appropriate error bit is set, and is stored in the fifo. if an overrun condition occurs, the overrun register bit is set immediately and the fifo data is pre- vented from being overwritten. uart1 also supports irda 1.0 (15.2 kbit/s). the modem status input signals clear to send (cts), data carrier detect (dcd) and data set ready (dsr) are supported on uart2 and uart3. timers two identical timers are integrated in the lh7a400. each of these timers has an associated 16-bit read/write data register and a control register. each timer is loaded with the value written to the data register immediately, this value will then be de cremented on the next active clock edge to arrive after the write. when the timer underflows, it will immediately assert its appropriate interrupt. the timers can be read at any time. the clock source and mode is selectable by writing to various bits in the system control register. clock sources are 508 khz and 2 khz. timer 3 (tc3) has the same basic operation, but is clocked from a single 7.3728 mhz source. it has the same register arrangement as timer 1 and timer 2, pro- viding a load, value, control and clear register. once the timer has been enabled and is written to, unlike the timer 1 and timer 2, will decrement the timer on the next rising edge of the 7.3728 mhz clock after the data register has been updated. all the timers can operate in two modes, free running mode or pre-scale mode. free-running mode in free-running mode, the timer will wrap around to 0xffff when it underflows and continue counting down. pre-scale mode in pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. this mode can be used to produce a pro- grammable frequency to drive the buzzer or generate a periodic interrupt.
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 33 real time clock (rtc) the rtc can be used to provide a basic alarm func- tion or long time-base counter. this is achieved by gen- erating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. counting in one second intervals is achieved by use of a 1 hz clock input to the rtc. battery monitor interface (bmi) the lh7a400 bmi is a serial communication inter- face specified for two type s of battery monitors/gas gauges. the first type employs a single wire interface. the second interface employs a two-wire multi-master bus, the smart battery system specification. if both interfaces are enabled at the same time, the single wire interface will have priority. a brief overview of these two interface types are given here. single wire interface the single wire interface performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion on data transmitted to the peripheral device data packet coding/decoding on data transfers (incorporating start/data/stop data packets) the single wire interface uses a command-based protocol, in which the host initiates a data transfer by sending a writedata/command word to the battery monitor. this word will always contain the command section, which tells the single wire interface device the location for the current transaction. the most signifi- cant bit of the command determines if the transaction is read or write. in the case of a write transaction, then the word will also cont ain a writedata section with the data to be written to the peripheral. smart battery interface the smbus interface performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion of data transmitted to the peripheral device. the smart battery interface uses a two-wire multi- master bus (the smbus), meaning that more than one device capable of controlling the bus can be connected to it. a master device initiates a bus transfer and provides the clock signals. a slave device can receive data pro- vided by the master or it can provide data to the master. since more than one device may attempt to take control of the bus as a master, smbus provides an arbitration mechanism, by relying on the wired-and connection of all smbus interfaces to the smbus. dc-to-dc converter the features of the dc-dc converter interface are: dual drive pwm outputs, with independent closed loop feedback software programmable configuration of one of 8 output frequencies (each being a fixed divide of the input clock). software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. output polarity (for positive or negative voltage gen- eration) is hardware-configured during power-on reset via the polarity select inputs each pwm output can be dynamically switched to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. watchdog timer (wdt) the watchdog timer provides hardware protection against malfunctions. it is a programmable timer that is reset by software at regular intervals. failure to reset the timer will cause a fiq inte rrupt. failure to service the fiq interrupt will then generate a system reset. the wdt features are: driven by the system clock 16 programmable time-out periods: 2 16 through 2 31 clock cycles generates a system reset (resets lh7a400) or a fiq interrupt whenever a time-out period is reached software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes protection mechanism guards against interrupt-service-failure: ? the first wdt time-out triggers fiq and asserts nwdfiq status flag ? if fiq service routine fails to clear nwdfiq, then the next wdt time-out triggers a system reset. general purpose i/o (gpio) the lh7a400 gpio has eight ports, each with a data register and a data direction register. it also has added registers including keyboard scan, pinmux, gpio interrupt enable, intype1/2, gpiofeoi and pghcon. the data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the gpio pins. the gpio interrupt enable, intype1/2, and gpi- ofeoi registers are used to control edge-triggered interrupts on port f. the pinmux register controls what signals are output of port d and port e when they are set as outputs, while the pghcon controls the operations of port g and h.
lh7a400 32-bit system-on-chip 34 12/8/03 preliminary data sheet electrical specifications absolute maximum ratings note: these ratings are only for trans ient conditions. operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. recommended operat ing conditions notes: 1. core voltage should never exceed i/o voltage. 2. usb is not functional below 3.0 v. 3. using 14.756 mhz main osci llator crystal and 32.768 khz rtc oscillator crystal. 4. vddc = 1.62 v to 1.98 v. 5. vdd = 3.0 v to 3.6 v. parameter minimum maximum dc core supply voltage (vddc) -0.3 v 2.4 v dc i/o supply voltage (vdd) -0.3 v 4.6 v dc analog supply voltage (vdda) -0.3 v 2.4 v storage temperature -55c 125c parameter minimum typical maximum notes dc core supply voltage (vddc) 1.62 v 1.8 v 1.98 v 1 dc i/o supply voltage (vdd) 3.0 v 3.3 v 3.6 v 2 dc analog supply voltage for plls (vdda) 1.62 v 1.8 v 1.98 v clock frequency (commercial) 10 mhz 200 mhz 3, 4, 5 clock frequency (industrial) 10 mhz 195 mhz 3, 4, 5 operating temperature (commercial) 0c 25c 70c operating temperature (industrial) -40c 25c +85c
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 35 dc/ac specifications (commercial and industrial) unless otherwise noted, all data provided under commercial dc/ac specifications are based on -40c to +85c, vddc = 1.62 v to 1.98 v, vdd = 3.0 v to 3.6 v, vdda = 1.62 v to 1.98 v. dc specifications notes: 1. output drive 5 can sink 20 ma of current, but sources 12 ma of current. 2. current consumption until oscillators are stabilized. ac test conditions symbol parameter min. typ. max. unit conditions notes vih cmos and schmitt trigger input high voltage 2.0 v vil cmos and schmitt tri gger input low voltage 0.8 v vhst schmitt trigger hysteresis 0.25 v vil to vih voh cmos output high voltage, output drive 1 2.6 v ioh = -2 ma output drive 2 2.6 v ioh = -4 ma output drive 3 2.6 v ioh = -8 ma output drive 4 and 5 2.6 v ioh = -12 ma 1 vol cmos output low voltage, output drive 1 0.4 v iol = 2 ma output drive 2 0.4 v iol = 4 ma output drive 3 0.4 v iol = 8 ma output drive 4 0.4 v iol = 12 ma output drive 5 0.4 v iol = 20 ma 1 iin input leakage current -10 10 a vin = vdd or gnd ioz output tri-state leakage current -10 10 a vout = vdd or gnd istartup startup current 50 a2 cin input capacitance 4 pf cout output capacitance 4 pf parameter rating unit dc i/o supply voltage (vdd) 3.0 to 3.6 v dc core supply voltage (vddc) 1.62 to 1.98 v input pulse levels vss to 3 v input rise and fall times 2 ns input and output timing reference levels vdd/2 v
lh7a400 32-bit system-on-chip 36 12/8/03 preliminary data sheet current consumption by operating mode current consumption can depend on a number of parameters. to make this data more usable, the values presented in table 7 were derived under the conditions presented here. maximum specified value the values specified in the maximum column were determined using these operating characteristics: all ip blocks either operating or enabled at maximum frequency and size configuration core operating at maximum power configuration all voltages at maximum specified values maximum specified ambient temperature. typical the values in the typical column were determined using a ?typical? application under ?typical? environmental conditions and the following operating characteristics: linux operating system running from sdram uart and ac97 peripherals operating; all other peripherals as needed by the os lcd enabled with 320 240 16-bit color, 60 hz refresh rate, data in sdram i/o loads at nominal cache enabled fclk = 200 mhz; hclk = 100 mhz; pclk = 50 mhz all voltages at typical values nominal case temperature. peripheral current consumption in addition to the modal current consumption, table 8 shows the typical current consumption for each of the on-board peripheral blocks. the values were deter- mined with the peripheral clock running at maximum frequency, typical conditions, and no i/o loads. this current is supplied by the 1.8 v power supply. table 7. current consumption by mode symbol parameter typ. max. units active mode icore current drawn by core 132 180 ma iio current drawn by i/o 15 58 ma halt mode (all peripherals disabled) icore current drawn by core 40 44 ma iio current drawn by i/o 1 1 ma standby mode (typical conditions only) icore current drawn by core 38 a iio current drawn by i/o 4 a table 8. peripheral current consumption peripheral typical units ac97 1.3 ma uart (each) 1.0 ma rtc 0.005 ma timers (each) 0.1 ma lcd (+i/o) 5.4 (1.0) ma mmc 0.6 ma sci 23 ma pwm (each) <0.1 ma bmi-swi 1.0 ma bmi-sbus 1.0 ma sdram (+i/o) 1.5 (14.8) ma usb (+pll) 5.6 (3.3) ma aci 0.8 ma
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 37 ac specifications all signals described in table 9 relate to transi- tions after a reference clock signal. the illustration in figure 6 represents all cases of these sets of mea- surement parameters. the reference clock signals in this design are: hclk, internal system bus clock (?c? in timing data) pclk, peripheral bus clock sspclk, synchronous serial port clock uartclk, uart interface clock lcddclk, lcd data clock from the lcd controller acbitclk, ac97 clock sclk, synchronous memory clock. all signal transitions are measured from the 50% point of the clock to the 50% point of the signal. for outputs from the lh7a400, tovxxx (e.g. tova) represents the amount of time for the output to become valid from a valid address bus, or rising edge of the peripheral clock. maximum requirements for tovxxx are shown in table 9. the signal tohxxx (e.g. toha) represents the amount of time the output will be held valid from the valid address bus, or rising edge of the peripheral clock. min- imum requirements for tohxxx are listed in table 9. for inputs, tisxxx (e.g. tisd) represents the amount of time the input signal must be valid after a valid address bus, or rising edge of the peripheral clock. max- imum requirements for tisxxx are shown in table 9. the signal tihxxx (e.g. tihd) represents the amount of time the output must be held valid from the valid address bus, or rising edge of the peripheral clock. minimum requirements are shown in table 9. figure 6. lh7a400 signal timing reference clock output signal (o) input signal (i) tovxxx tohxxx tisxxx tihxxx 7a400-28
lh7a400 32-bit system-on-chip 38 12/8/03 preliminary data sheet table 9. ac signal characteristics signal type load symbol min. max. description asynchronous memory interface signals (+ wait states c) 1 d[31:0] output 50 pf tovd 1c + 1 ns data valid tohd 3c ? 7 ns data hold input tisd 3c ? 20 ns data setup tihd 3c ? 3 ns data hold ncs[3:0]/cs[7:6] output 30 pf tovcsr 0 ns chip select valid (read) tovcsw 1c chip select valid (write) tohcs 3c ? 10 ns chip select hold nwe[3:0] output 30 pf tovwe 1c write enable valid tohwe 2c ? 10 ns write enable hold tohwecs 0 1c deassertion delay between nwe[3:0] and ncs[3:0]/cs[7:6] noe output 30 pf tovoe 1c ouput enable valid tohoe 3c ? 10 ns ouput enable hold synchronous memory interface signals sa[13:0] output 50 pf tova 7.5 ns address valid sa[17:16]/sb[1:0] output 50 pf tovb 7.5 ns bank select valid d[31:0] output 50 pf tovd 2 ns 7.5 ns data valid input tisd 2 ns data setup tihd 1 ns data hold ncas output 30 pf tovca 2 ns 7.5 ns cas valid tohca 0.0 ns cas hold nras output 30 pf tovra 2 ns 7.5 ns ras valid tohra 0.0 ns ras hold nswe output 30 pf tovsdw 2 ns 7.5 ns write enable valid tohsdw 0.0 ns write enable hold scke[1:0] output 30 pf tovc 2 ns 7.5 ns clock enable valid dqm[3:0] output 30 pf tovdq 2 ns 7.5 ns data mask valid nscs[3:0] output 30 pf tovsc 2 ns 7.5 ns synchronous chip select valid tohsc 0.0 ns synchronous chip select hold pcmcia interface signals (+ wait states c) 1 npcreg output 30 pf tovdreg 1c nreg valid tohdreg 4c ? 5 ns nreg hold d[31:0] output 50 pf tovd 1c data valid tohd 4c ? 5 ns data hold input tisd 1c data setup time tihd 4c ? 15 ns data hold time npcce1 output 30 pf tovce1 1c chip enable 1 valid tohce1 4c ? 5 ns chip enable 1 hold npcce2 output 30 pf tovce2 1c chip enable 2 valid tohce2 4c ? 5 ns chip enable 2 hold npcoe output 30 pf tovoe 1c + 1 ns output enable valid tohoe 3c ? 5 ns output enable hold npcwe output 30 pf tovwe 1c + 1 ns write enable valid tohwe 3c ? 5 ns write enable hold pcdir output 30 pf tovpcd 1c card direction valid tohpcd 4c ? 5 ns card direction hold mmc interface signals mmccmd output 100 pf tovcmd 3 ns mmc command valid tohcmd 3 ns mmc command hold mmcdata output 100 pf tovdat 3 ns mmc data valid tohdat 3 ns mmc data hold
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 39 notes: 1. ?nc? in the min./max. columns indicates the number of system clock (hclk) periods after valid address. 2. for output drive strength spec ifications, refer to table 1. mmcdata input tisdat 5 ns mmc data setup tihdat 5 ns mmc data hold mmccmd input tiscmd 5 ns mmc command setup tihcmd 5 ns mmc command hold ac97 interface signals acout/acsync output 30 pf tovac97 15 ns ac97 output valid/sync valid tohac97 10 ns ac97 output hold/sync hold acin input tisac97 10 ns ac97 input setup tihac97 2.5 ns ac97 input hold acbitclk input tacbitclk 72 ns 90 ns ac97 clock period synchronous serial port (ssp) sspfrm input tissspfrm 14 ns sspfrm input valid ssptx output 50 pf tovsspout 14 ns ssp transmit valid ssprx input tissspin 14 ns ssp receive setup audio codec interface (aci) acout/acsync output 30 pf tos tbd tbd acout delay from rising clock edge toh tbd tbd acout hold acin input tis tbd tbd acin setup tih tbd tbd acin hold table 9. ac signal characteristics (cont?d) signal type load symbol min. max. description
lh7a400 32-bit system-on-chip 40 12/8/03 preliminary data sheet smc waveforms figure 7 shows the waveform and timing for an external asynchronous memory write. note that the deassertion of nwe can preceed the deassertion of ncs by a maximum of one hclk, or at minimum, can coincide (see table 9). figure 8 shows the waveform and timing for an external asynchronous memory read, with one wait state. figure 7. external asynchronous memory write figure 8. external asynchronous memory read hclk (see note 2) address data a[27:0] (see note 1) d[31:0] ncsx, csx nwe[3:0] t ovd t ohd t ovcsw t ohcs t ovwe t ohwe t ohwecs lh7a400-20 notes: 1. a[24:0] when sci used. 2. hclk is an internal signal, shown for reference only. 0123 4 hclk (see note) address data a[25:0] d[31:0] ncsx, csx noe t isd t ihd t ohcs t ovcsr t ovoe t ohoe lh7a400-21 note: hclk is an internal signal, shown for reference only. 0123
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 41 synchronous memory controller waveforms figure 9 shows the waveform and timing for a syn- chronous burst read (page already open). figure 10 shows the waveform and timing for synchronous mem- ory to activate a bank and write. figure 9. synchronous burst read figure 10. synchronous bank activate and write t sclk lh7a400-23 sa[13:0], sb[1:0] d[31:0] notes: 1. sdramcmd is the combination of nras, ncas, nswe, and nscsx. 2. tovxxx represents tovra, tovca, tovsvw, or tovsc. 3. tohxxx represents tohra, tohca, tohsvw, or tohsc. 4. dqm[3:0] is static low. 5. scke is static high. sclk sdramcmd ndqm t ovxxx t ova t ohxxx read bank, column tova tisd tihd data n data n + 1 data n + 2 data n + 3 lh7a400-24 d[31:0] sclk scke sdramcmd tsclk tovc tovxxx tova tohxxx tova notes: 1. sdramcmd is the combination of nras, ncas, nswe, and nscsx. 2. tovxxx represents tovra, tovca, tovsvw, or tovsc. refer to the ac timing table. 3. tohxxx represents tohra, tohca, tohsvw, or tohsc. 4. dqm[3:0] is static low. active write data bank, row bank, column tovd tohd sa[13:0], sb[1:0]
lh7a400 32-bit system-on-chip 42 12/8/03 preliminary data sheet pc card (pcmcia) waveforms figure 11 shows the waveforms and timing for a pcmcia read transfer, figure 12 shows the wave- forms and timing for a pcmcia write transfer. figure 11. pcmcia read transfer tovdreg hclk a[25:0] tovpcd tisd tohdreg address precharge time (see note 1) access time (see note 1) hold time (see note 1) data tihd tovcex tohcex lh7a400-11 npcreg npccex (see note 2) pcdir d[15:0] npcoe notes: 1. precharge time, access time, and hold time are programmable wait-state times. 2. npcce1 0 0 1 1 npcce2 0 1 0 1 transfer type common memory attribute memory i/o none tovoe tohoe
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 43 figure 12. pcmcia write transfer tovdreg hclk a[25:0] tovpcd tovd tovwe tohdreg address precharge time (see note 1) access time (see note 1) hold time (see note 1) data tohd tohwe tovcex tohcex lh7a400-12 npcreg npccex (see note 2) pcdir d[15:0] npcwe notes: 1. precharge time, access time, and hold time are programmable wait-state times. 2. npcce1 0 0 1 1 npcce2 0 1 0 1 transfer type common memory attribute memory i/o none
lh7a400 32-bit system-on-chip 44 12/8/03 preliminary data sheet mmc interface waveforms figure 13 shows the waveforms and timing for an mmc command or data write, and figure 14 shows the waveforms and timing for an mmc command or data read. ac97 interface waveforms figure 15 shows the waveforms and timing for the ac97 interface data setup and hold. figure 13. mmc command/data write figure 14. mmc command/data read figure 15. ac97 data setup and hold tovcmd mmcclk mmccmd mmcdat tohcmd tovdat tohdat lh7a400-14 tiscmd mmcclk mmccmd mmcdat tihcmd tisdat tihdat lh7a400-15 lh7a400-16 tovac97 acbitclk acout/acsync acin tisac97 tihac97 tohac97 tacbitclk
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 45 audio codec in terface waveforms figure 16 and figure 17 show the timing for the aci. transmit data is clocked on the rising edge of acbitclk (whether transmitted by the lh7a404 aci or by the external codec chip ); receive data is clocked on the falling edge. this allows full-speed, full duplex operation. figure 16. aci signal timing figure 17. aci datastream tos tis tih toh acbitclk acsync/acout acin lh7a400-169 lh7a400-181 acbitclk acsync acin/acout acin/acout sampled on falling edge 76 bit 5 4 3 2 1 0 7 6
lh7a400 32-bit system-on-chip 46 12/8/03 preliminary data sheet clock and state controller (csc) waveforms figure 18 shows the behavior of the lh7a400 when coming out of reset or power on. figure 19 shows exter- nal reset timing, and table 10 gives the timing parame- ters. figure 20 depicts signal timing following a reset. figure 21 shows the recommended components for the sharp lh7a400 32.768 khz external oscillator circuit. figure 22 shows the same for the 14.7456 mhz external oscillator circuit. in both figures, the nand gate represents the internal logic of the chip. note: *vddc = vddcmin table 10. reset ac timing parameter description min. max. unit tosc32 32 khz oscillator stabilization time after power on* 550 ms tporh npor hold time after tosc32 0 ms tosc14 14.7456 mhz oscillator stabilization time after wake up 4 ms tplll phase locked loop lockup time 250 s tureset/tpwrfl nureset/npwrfl pulse width (once sampled low) 2 system clock cycles figure 18. oscillator start-up figure 19. external reset lh7a400-25 tosc32 tosc14 tporh vddc vddcmin xtal32 npor xtal14 lh7a400-26 tureset tpwrfl nureset npwrfl
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 47 figure 20. signal timing after reset figure 21. 32.768 khz external oscillator components and schematic 7.8125 ms 7.8125 ms start up wakeup (asynchronous) clken hclk stable clock lh7a400-175 enable xtalin xtalout gnd notes: 1. y1 is a parallel-resonant type crystal. (see table) 2. the nominal values for c1 and c2 shown are for a crystal specified at 12.5 pf load capacitance (cl). 3. the values for c1 and c2 are dependent upon the cystal's specified load capacitance and pcb stray capacitance. 4. r1 must be in the circuit. 5. ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. tolerance for r1, c1, c2 is 5%. gnd 32.768 khz 18 m ? lh7a400-187 parameter description 32.768 khz crystal tolerance aging load capacitance esr (max.) drive level recommended part parallel mode 30 ppm 3 ppm 12.5 pf 50 k ? 1.0 w (max.) mtron sx1555 or equivalent c1 15 pf c2 18 pf r1 y1 internal to the lh7a400 external to the lh7a400 recommended crystal specifications
lh7a400 32-bit system-on-chip 48 12/8/03 preliminary data sheet figure 22. 14.7456 mhz external oscillator components and schematic enable xtalin xtalout gnd notes: 1. y1 is a parallel-resonant type crystal. (see table) 2. the nominal values for c1 and c2 shown are for a crystal specified at 18 pf load capacitance (cl). 3. the values for c1 and c2 are dependent upon the cystal's specified load capacitance and pcb stray capacitance. 4. r1 must be in the circuit. 5. ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. tolerance for r1, c1, c2 is 5%. gnd 14.7456 mhz 1 m ? lh7a400-188 c1 18 pf c2 22 pf r1 y1 internal to the lh7a400 external to the lh7a400 parameter description 14.7456 mhz crystal tolerance stability aging load capacitance esr (max.) drive level recommended part (at-cut) parallel mode 50 ppm 100 ppm 5 ppm 18 pf 40 ? 100 w (max.) mtron sx2050 or equivalent recommended crystal specifications
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 49 printed circuit b oard layout practices lh7a400 power supply decoupling the lh7a400 has separate power and ground pins for different internal circuitry sections. the vdd and vss pins supply power to i/o buffers, while vddc and vssc supply power to the co re logic, and vdda/vssa supply analog power to the plls. each of the vdd and vddc pins must be provided with a low impedance path to the corresponding board power supply. likewise, the vss and vssc pins must be provided with a low impedance path to the board ground. each power supply must be decoupled to ground using at least one 0.1 f high frequency capacitor located as close as possible to a vddx, vssx pin pair on each of the four sides of the chip. if room on the cir- cuit board allows, add one 0.01 f high frequency capacitor near each vddx , vssx pair on the chip. to be effective, the capacitor leads and associated circuit board traces connecting to the chip vddx, vssx pins must be kept to less than half an inch (12.7 mm) per capacitor lead. there must be one bulk 10 f capacitor for each power supply placed near one side of the chip. required lh7a400 pll, vdda, vssa filter the vdda pins supplies power to the chip pll cir- cuitry. vssa is the ground re turn path for the pll cir- cuit. these pins must have a low-pass filter attached as shown in figure 23. the schottky diode shown in the schematic must have a low forward drop specification to allow vdda to quickly transition through the entire input voltage range. the power pin vdda path must be a single wire from the ic package pin to the high frequency capaci- tor, then to the low frequency capacitor, and finally through the series resistor to the board power supply. the distance from the ic pin to the high frequency capacitor must be kept as short as possible. similarly, the vssa path is from the ic pin to the high frequency capacitor, then to the low frequency capacitor, keeping the distance from the ic pin to the high frequency cap as short as possible. unused input signal conditioning floating input signals can cause excessive power consumption. unused inputs without internal pull-up or pull-down resistors should be pulled up or down exter- nally, to tie the signal to its inactive state. some gpio signals may default to inputs. if the pins that carry these signals are unused, software can pro- gram these signals as outputs, eliminating the need for pull-ups or pull-downs. power consumption may be higher than expected until software completes pro- gramming the gpio. some lh7a400 inputs have inter- nal pull-ups or pull-downs. if unused, these inputs do not require external conditioning. other circuit board layout practices all outputs have fast rise and fall times. printed cir- cuit trace interconnection length must therefore be reduced to minimize overshoo t, undershoot and reflec- tions caused by transmission line effects of these fast output switching times. this recommendation particu- larly applies to the address and data buses. when considering capacitance, calculations must consider all device loads and capacitances due to the circuit board traces. capacit ance due to the traces will depend upon a number of factors, including the trace width, dielectric material the circuit board is made from and proximity to ground and power planes. attention to power supply decoupling and printed cir- cuit board layout becomes mo re critical in systems with higher capacitive loads. as these capacitive loads increase, transient currents in the power supply and ground return paths also increase. note that the vssa pin specifically does not have a connec- tion to the circuit board ground. the lh7a400 pll circuit has an internal dc ground connection to vss (gnd), so the ex- ternal vssa pin must not be connected to the circuit board ground, but only to the filter components. caution figure 23. vdda, vssa filter circuit lh7a400-189 vdda vddc vssa 22 f 100 ? vddc (source) 0.1 f + lh7a400
lh7a400 32-bit system-on-chip 50 12/8/03 preliminary data sheet package specifications figure 24. 256-ball pbga package specification 1.00 1.00 ref. 15.00 +0.70 -0.05 15.00 +0.70 -0.05 +0.10 -0.10 6.00 2.90 6.00 2.90 11.64 max. 1.21 typ. 1.21 typ. 11.64 max. bottom view (256 solder balls) side view top view 1.00 ref. 0.50 r, 3 places note : dimensions in mm. c ca c b 0.30 m 0.50 0.10 m c 0.15 0.80 0.05 0.40 0.10 1.76 0.21 seating plane 1.56 0.06 1.00 b a1 ball pad corner 15 13 11 9 7 5 3 a b c d e f g h j k l m n p r t 1 16 30? typ. 14 12 10 8 6 4 2 a (4x) 0.20 c 0.25 c 0.35 17.00 17.00 256-ball pbga a1 ball pa d corner a1 ball pad indicator, 1.0 dia. available marking area 45 ? chamfer 4 places 256pbga
32-bit system-on-chip lh7a400 preliminary data sheet 12/8/03 51 figure 25. 256-ball cabga package specification 0.80 1.0 1.0 bottom view (256 solder balls) side view top view c c 5 a c b 0.15 m 0.46 typ. 0.08 m c 0.12 0.36 0.04 0.70 0.05 seating plane 1.70 max. 0.80 b 15 13 11 9 7 5 3 a b c d e f g h j k l m n p r t 1 14 12 10 8 16 6 4 2 a (4x) 0.10 c 0.10 14.00 14.00 a1 ball pad corner 256-ball cabga 256cabga 6 note : dimensions in mm.
lh7a400 32-bit system-on-chip 52 12/8/03 preliminary data sheet ordering information note: *requires factory approval. content revisions this document contains the following changes to content, causing it to differ from previous versions. table 11. ordering information part number package speed (mhz) at temp. (c) lh7a400n0b000 pbga 200 at 0+70 195 at -40+85 lh7a400n0e000 cabga 200 at 0+70 195 at -40+85 LH7A400N0C000* scribed die 200 at 0+70 195 at -40+85 lh7a400n0w000* probed wafer 200 at 0+70 195 at -40+85 table 12. record of revisions date page no. paragraph or illustration summary of changes 8-19-2003 1 features 256-ball cabga package added 3-11 table 1 cabga pins added; vdda1/vdda2 combined to vdda; vssa1/vssa2 combined to vssa 12 table 3 signal ordering corrected 12-18 table 4 table title added to differentiate between pbga and cabga packages 18-24 table 5 cabga numerical pin list table added 39 figure 7 and figure 8 ?csx? added to figures 41-42 figures 11 and 12 pcdir signal corrected in pcmcia timing diagrams 44 table 10 and figure 16 tosc14 added to both table and figure; xtal14 added to figure; tplll added to table 45-47 figures 19-21 and printed circuit board layout practices figures and text added 49 figure 23 figure added for cabga package 11-15-03 1text corrected minor text errors; added separate commercial and industrial temperature specification. 2 figure 1 updated to show ali interface 34 ?recommended operating conditions? broke out ?commercial? and ?industrial? speed ranges. 37-38 table 9 minor corrections to type. 39 table 9 added aci timing. 49 figure 24 pbga package drawing added. 51 table 11 added ordering information
32-bit system-on-chip lh7a400 ?2003 by sharp corporation reference code sma01012 specifications are subject to change without notice. suggested applications (if any) are for standard use; see important restrictions for limitations on special applications. see l imited warranty for sharp?s product warranty. the limited warranty is in lieu, and exclusive of, all other warranties, express or impl ied. all express and implied warranties, including the warranties of merchantability, fitness for use and fitness for a particular purpose, are specifically excluded. in no event will sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. north america europe japan sharp microelectronics of the americas 5700 nw pacific rim blvd. camas, wa 98607, u.s.a. phone: (1) 360-834-2500 fax: (1) 360-834-8903 www.sharpsma.com sharp microelectronics europe division of sharp electronics (europe) gmbh sonninstrasse 3 20097 hamburg, germany phone: (49) 40-2376-2286 fax: (49) 40-2376-2232 www.sharpsme.com sharp corporation electronic components & devices 22-22 nagaike-cho, abeno-ku osaka 545-8522, japan phone: (81) 6-6621-1221 fax: (81) 6117-725300/6117-725301 www.sharp-world.com taiwan singapore korea sharp electronic components (taiwan) corporation 8f-a, no. 16, sec. 4, nanking e. rd. taipei, taiwan, republic of china phone: (886) 2-2577-7341 fax: (886) 2-2577-7326/2-2577-7328 sharp electronics (singapore) pte., ltd. 438a, alexandra road, #05-01/02 alexandra technopark, singapore 119967 phone: (65) 271-3566 fax: (65) 271-3855 sharp electronic components (korea) corporation rm 501 geosung b/d, 541 dohwa-dong, mapo-ku seoul 121-701, korea phone: (82) 2-711-5813 ~ 8 fax: (82) 2-711-5819 china hong kong sharp microelectronics of china (shanghai) co., ltd. 28 xin jin qiao road king tower 16f pudong shanghai, 201206 p.r. china phone: (86) 21-5854-7710/21-5834-6056 fax: (86) 21-5854-4340/21-5834-6057 head office: no. 360, bashen road, xin development bldg. 22 waigaoqiao free trade zone shanghai 200131 p.r. china email: smc@china.global.sharp.co.jp sharp-roxy (hong kong) ltd. 3rd business division, 17/f, admiralty centre, tower 1 18 harcourt road, hong kong phone: (852) 28229311 fax: (852) 28660779 www.sharp.com.hk shenzhen representative office: room 13b1, tower c, electronics science & technology building shen nan zhong road shenzhen, p.r. china phone: (86) 755-3273731 fax: (86) 755-3273735

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